The invention relates to pass gate multiplexer circuits susceptible to single event upsets, such as those in programmable logic devices (PLDs). More particularly, the invention relates to pass gate multiplexer circuits on which single event upsets have a reduced impact.
Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). Some FPGAs also include additional logic blocks with special purposes (e.g., DLLs, RAM, and so forth).
The various logic blocks are interconnected by a programmable interconnect structure that includes a large number of programmable interconnect lines (e.g., metal wires). The interconnect lines and logic blocks are interconnected using programmable interconnect points (PIPs). A PIP can be, for example, a pass gate. When the pass gate is turned on, the two nodes on either side of the pass gate are electrically connected. When the pass gate is turned off, the two nodes are isolated from each other. Thus, by controlling the values on the gate terminals of the pass gates, circuit connections can easily be made and altered.
The logic blocks and PIPs in a PLD are typically programmed (configured) by loading configuration data into thousands of configuration memory cells. In Field Programmable Gate Arrays (FPGAs), for example, each configuration memory cell is implemented as a static RAM cell. These static RAM cells are used, for example, to control the gate terminals of pass gates between pairs of interconnect lines.
When subjected to unusual conditions such as cosmic rays or bombardment by neutrons or alpha particles, a static RAM cell can change state. For example, a stored high value can be inadvertently changed to a low value, and vice versa. Sometimes these xe2x80x9csingle event upsetsxe2x80x9d have no effect on the functionality of the chip, for example, when the static RAM cell controls a pass gate between two unused interconnect lines. At other times, a single event upset can change the functionality of a configured PLD such that the circuit no longer functions properly.
FIG. 1 shows an exemplary PLD circuit that is subject to the effects of single event upsets. The circuit of FIG. 1 is a multiplexer circuit that includes several pass gates. This type of circuit is commonly included in FPGA interconnect structures, for example. The circuit selects one of several different input signals and passes the selected signal to an output node.
The circuit of FIG. 1 includes eight input terminals IN0-IN7 and eight pass gates 100-107 that selectively pass one of signals IN0-IN7, respectively, to an internal node INT. (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.) The signal on internal node INT is buffered by buffer BUF to provide output signal OUT. Buffer BUF, for example, can include two inverters 111, 112 coupled in series, and a pull up (e.g., a P-channel transistor 113 to power high VDD) on internal node INT and driven by the node between the two inverters. However, buffer BUF can be implemented in many different ways.
Each pass gate 100-107 has a gate terminal driven by a memory cell M0-M7, respectively. Each memory cell can include two cross-coupled inverters An, Bn, for example. However, memory cell M0-M7 can also be implemented in many different ways. For example, configuration memory cells in FPGAs typically include configuration logic for loading the configuration data. The details of memory cells M0-M7 are omitted, for clarity.
The multiplexer circuit of FIG. 1 operates as shown in Table 1. At most, one of memory cells M0-M7 can be configured with a high value at any given time. Other configurations are not supported by the circuit. As shown in Table 1, the one memory cell with a high value selects the associated input signal IN0-IN7 to be passed to internal node INT, and hence to output node OUT. If none of memory cells M0-M7 is configured with a high value, output signal OUT is held at its initial high value by pullup 113.
In the multiplexer circuit of FIG. 1, the upset of any single memory cell (i.e., any single event upset affecting any of memory cells M0-M7) causes a failure in the circuit. For example, assume that memory cell M0 stores a high value, while memory cells M1-M7 store low values. Pass gate 100 is enabled, and the selected input signal is IN0. Pass gates 101-107 are disabled. If the value in memory cell M4 is upset (i.e., changes to a high value), pass gate 104 is enabled and there is a xe2x80x9cshortxe2x80x9d (an inadvertent coupling) between input terminals IN0 and IN4. Similarly, if the value in memory cell M5 is upset, pass gate 105 is enabled and there is a short between nodes IN0 and IN5, and so forth. If the value in memory cell M0 is upset (i.e., changes to a low value), the path from input terminal IN0 to output terminal OUT is broken, and output signal OUT is no longer actively driven by node IN0.
Thus, the multiplexer structure of FIG. 1 is susceptible to single event upsets. Further, as operating voltages diminish, static RAM cells become more susceptible to changes in state caused by single event upsets. To reduce manufacturing costs, PLD manufacturers are aggressively reducing device sizes in their PLDs. These smaller devices often operate at lower voltages. Therefore, the effects of single event upsets are becoming more important over time. It is desirable to provide PLD circuits with reduced susceptibility to single event upsets, particularly commonly-used circuits such as multiplexing circuits.
The invention provides multiplexer circuits for programmable logic devices (PLDS) that have reduced susceptibility to single event upsets. A standard pass gate multiplexer circuit having N pass gates and N memory cells controlling the pass gates is modified to include an additional N pass gates, one on each input path. Thus, each path between an input terminal and the output node includes two pass gates controlled by different memory cells.
Therefore, a single event upset that inadvertently enables a pass gate can only short together two input terminals when the other pass gate in the affected input path is also enabled by its associated memory cell. Hence, an upset in any one of four memory cells still creates a circuit error. (The four pass gates that can create a circuit error are the two on the selected input path, which should be enabled, and two that should be disabled that are coupled in series with two other pass gates sharing memory cells with the pass gates on the selected path.) Therefore, the multiplexer circuit of the invention reduces the susceptibility to single event upsets by a factor of (Nxe2x88x924)/N.
A first multiplexer circuit according to the invention includes N input circuits, N memory cells susceptible to single event upsets, and an output node. N is an integer greater than four. Each input circuit includes an input terminal, a first pass gate coupled to the first input terminal, a second pass gate coupled to the first pass gate, and an output terminal coupled to the second pass gate. The output node is coupled to each output terminal of the N input circuits. Each of the N memory cells is coupled to the gate terminal of a pass gate in each of two different input circuits.
Some embodiments also include an output buffer coupled to the output node. In some embodiments, N is eight. In some embodiments, the pass gates are implemented as N-channel transistors.
A second multiplexer circuit according to the invention includes N input terminals, an output node, N first pass gates coupled between the N input terminals and the output node, and N second pass gates. N is an integer greater than four. Each second pass gate is coupled in series with one of the N first pass gates to form a pass gate pair. Each of the N memory cells is coupled to gate terminals of one of the N first pass gates and one of the N second pass gates. Each pass gate pair includes two pass gates having gate terminals coupled to different ones of the N memory cells.
A third embodiment of the invention is a system controlled by memory cells susceptible to single event upsets. The system includes programmable logic blocks, interconnect lines, and multiplexer circuits programmably coupling the interconnect lines to each other and to the logic blocks. Each multiplexer circuit includes the elements and circuit configuration described above with reference to the second multiplexer circuit.
In one embodiment, the system is a programmable logic device (PLD). In one such embodiment, the PLD is a field programmable gate array (FPGA) and the memory cells are configuration memory cells containing configuration data for the FPGA.